Validation of Task Scheduling Techniques in Multithread Time Predictable Systems

This paper presents a simulation-based environment for verification of static task scheduling methodology in time predictable system. Different types processed tasks are distinguished and presented unified system design consisting the selection real configuration, mapping, scheduling, generation sequence identifiers to control interleaved pipeline. An original Worst Case Timing Analyzer (WCTA) has been developed automate process. The was introduced into PRET (PREcision Timed) architecture recently (Antolak Pulka, 2020), 2021). implemented on Virtex7 FPGA (Field Programmable Gate Array) platform. A dedicated is proposed that allows on-line monitoring, analysis timing parameters, comparing results with initial requirements constraints. practical experiments proved correct operation author’s hardware architecture. obtained confirmed validity method concept calculating execution times before they started, which optimal matching be performed.